Semiconductor device, method of manufacturing semiconductor device, inverter circuit, driving device, vehicle, and elevator

ABSTRACT

A semiconductor device according to an embodiment includes: a SiC layer having a first plane, a second plane, a first trench located on a first plane side, an n-type first SiC region, a p-type second SiC region between the first SiC region and the first plane, an n-type third SiC region between the second SiC region and the first plane, and a p-type fourth SiC region between the first SiC region and the first plane, at least a portion of the fourth SiC region located in the second SiC region, the fourth SiC region having a higher p-type impurity concentration than the second SiC region; a gate electrode in the first trench; a first electrode located on the first plane side; and a second electrode located on a second plane side. A depth of the fourth SiC region increases with distance from the first trench.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromJapanese Patent Application No. 2019-167646, filed on Sep. 13, 2019, theentire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device,a method of manufacturing a semiconductor device, an inverter circuit, adriving device, a vehicle, and an elevator.

BACKGROUND

Silicon carbide (SiC) is expected as a material for next-generationsemiconductor devices. The silicon carbide has excellent physicalproperties such as a band gap of about 3 times, a breakdown fieldstrength of about 10 times, and a thermal conductivity of about 3 timesas compared with silicon. By utilizing these physical properties, it ispossible to realize a semiconductor device capable of operating at a lowloss and at a high temperature.

In a vertical-type metal oxide semiconductor field effect transistor(MOSFET), a trench gate structure in which a gate electrode is providedin a trench is applied in order to realize a low on-resistance. Byapplying the trench gate structure, the channel area per unit areaincreases, and the on-resistance is reduced. It can be expected that theon-resistance is further reduced by shortening the channel length.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a semiconductor deviceaccording to a first embodiment;

FIG. 2 is a schematic plan view of the semiconductor device according tothe first embodiment;

FIG. 3 is an enlarged schematic cross-sectional view of thesemiconductor device according to the first embodiment;

FIG. 4 is a view illustrating an impurity concentration distribution ofthe semiconductor device according to the first embodiment;

FIG. 5 is a schematic cross-sectional view illustrating an example of amethod of manufacturing the semiconductor device according to the firstembodiment;

FIG. 6 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 7 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 8 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 9 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 10 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 11 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 12 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 13 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 14 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 15 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 16 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 17 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 18 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 19 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thefirst embodiment;

FIG. 20 is a schematic cross-sectional view of a semiconductor deviceaccording to Comparative Example;

FIG. 21 is a schematic cross-sectional view illustrating an example of amethod of manufacturing the semiconductor device according to a secondembodiment;

FIG. 22 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thesecond embodiment;

FIG. 23 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thesecond embodiment;

FIG. 24 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thesecond embodiment;

FIG. 25 is a schematic cross-sectional view of a semiconductor deviceaccording to a third embodiment;

FIG. 26 is a schematic cross-sectional view illustrating an example of amethod of manufacturing the semiconductor device according to the thirdembodiment;

FIG. 27 is a schematic cross-sectional view illustrating an example ofthe method of manufacturing the semiconductor device according to thethird embodiment;

FIG. 28 is a schematic view of a driving device according to a fourthembodiment;

FIG. 29 is a schematic view of a vehicle according to a fifthembodiment;

FIG. 30 is a schematic view of a vehicle according to a sixthembodiment; and

FIG. 31 is a schematic view of an elevator according to a seventhembodiment.

DETAILED DESCRIPTION

A semiconductor device according to an embodiment includes: a siliconcarbide layer having a first plane parallel to a first direction and asecond direction perpendicular to the first direction and a second planefacing the first plane, the silicon carbide layer having a first trenchbeing located on a side of the first plane and extending in the firstdirection, a first silicon carbide region of n-type, a second siliconcarbide region of p-type being located between the first silicon carbideregion and the first plane, a third silicon carbide region of n-typebeing located between the second silicon carbide region and the firstplane, and a fourth silicon carbide region of p-type being locatedbetween the first silicon carbide region and the first plane, at least aportion of the fourth silicon carbide region being located in the secondsilicon carbide region, the fourth silicon carbide region having ahigher p-type impurity concentration than a p-type impurityconcentration of the second silicon carbide region; a gate electrodebeing located in the first trench; a gate insulating layer being locatedbetween the gate electrode and the silicon carbide layer; a firstelectrode being located on a side of the first plane of the siliconcarbide layer; and a second electrode being located on a side of thesecond plane of the silicon carbide layer, wherein a first position anda second position exist in the at least portion of the fourth siliconcarbide region, a first distance from the first plane to the firstposition is smaller than a second distance from the first plane to thesecond position, and a third distance from the gate insulating layer tothe first position is smaller than a fourth distance from the gateinsulating layer to the second position.

Hereinafter, embodiments will be described with reference to thedrawings. In addition, in the following description, the same or similarmembers are denoted by the same reference numerals, and the descriptionof the members or the like that have been described once is omitted asappropriate.

In addition, in the following description, the notations n⁺, n, n⁻ andp⁺, p, p⁻ represent the relative levels of the impurity concentrationsin the respective conductivity types. That is, n⁺ represents to berelatively higher in the n-type impurity concentration than n, and n⁻represents to be relatively lower in the n-type impurity concentrationthan n. In addition, p⁺ represents to be relatively higher in the p-typeimpurity concentration than p, and p⁻ represents to be relatively lowerin the p-type impurity concentration than p. In addition, in some cases,the n⁺-type and the n⁻-type may be simply referred to as the n-type andthe p⁺-type and p⁻-type may be simply referred to as the p-type.

The impurity concentration can be measured by, for example, secondaryion mass spectrometry (SIMS). In addition, the relative level of theimpurity concentration can be determined from the level of the carrierconcentration obtained by, for example, scanning capacitance microscopy(SCM). In addition, the distance such as the width and depth of theimpurity region can be obtained by, for example, SIMS. In addition, thedistance such as the width and depth of the impurity region can beobtained from, for example, an SCM image.

The depth of the trench, the thickness of the insulating layer, and thelike can be measured on images of, for example, a transmission electronmicroscope (TEM). In addition, for example, the depth of the trench, thethickness of the insulating layer, and the like can be determined from aSIMS profile.

In this specification, the “p-type impurity concentration” of the p-typesilicon carbide region denotes a net p-type impurity concentrationobtained by subtracting the n-type impurity concentration of the regionfrom the p-type impurity concentration of the region. In addition, the“n-type impurity concentration” of the n-type silicon carbide regiondenotes a net n-type impurity concentration obtained by subtracting thep-type impurity concentration of the region from the n-type impurityconcentration of the region.

First Embodiment

A semiconductor device according to a first embodiment includes: asilicon carbide layer having a first plane parallel to a first directionand a second direction perpendicular to the first direction and a secondplane facing the first plane, the silicon carbide layer having a firsttrench being located on a side of the first plane and extending in thefirst direction, a first silicon carbide region of n-type, a secondsilicon carbide region of p-type being located between the first siliconcarbide region and the first plane, a third silicon carbide region ofn-type being located between the second silicon carbide region and thefirst plane, and a fourth silicon carbide region of p-type being locatedbetween the first silicon carbide region and the first plane, at least aportion of the fourth silicon carbide region being located in the secondsilicon carbide region, the fourth silicon carbide region having ahigher p-type impurity concentration than a p-type impurityconcentration of the second silicon carbide region; a gate electrodebeing located in the first trench; a gate insulating layer being locatedbetween the gate electrode and the silicon carbide layer; a firstelectrode being located on a side of the first plane of the siliconcarbide layer; and a second electrode being located on a side of thesecond plane of the silicon carbide layer. A first position and a secondposition exist in the at least portion of the fourth silicon carbideregion, a first distance from the first plane to the first position issmaller than a second distance from the first plane to the secondposition, and a third distance from the gate insulating layer to thefirst position is smaller than a fourth distance from the gateinsulating layer to the second position.

The semiconductor device according to the first embodiment is avertical-type MOSFET 100 using silicon carbide. The MOSFET 100 is aMOSFET having a trench gate structure in which a gate electrode isprovided in a trench. The MOSFET 100 is a MOSFET having a so-calleddouble trench structure in which a source electrode is provided in atrench. The MOSFET 100 is an n-channel MOSFET using electrons ascarriers.

FIG. 1 is a schematic cross-sectional view of the semiconductor deviceaccording to the first embodiment. FIG. 2 is a schematic plan view ofthe semiconductor device according to the first embodiment. FIG. 3 is anenlarged schematic cross-sectional view of the semiconductor deviceaccording to the first embodiment.

FIG. 1 is an AA′ cross-sectional view of FIG. 2. FIG. 2 illustrates apattern on the first plane P1 of FIG. 1. FIG. 3 is an enlarged view of aportion of FIG. 1.

The MOSFET 100 includes a silicon carbide layer 10, a source electrode12 (first electrode), a drain electrode 14 (second electrode), a gateelectrode 16, a gate insulating layer 18, and an interlayer insulatinglayer 20. The source electrode 12 has a contact region 12 a.

The silicon carbide layer 10 includes a gate trench 21 (first trench), acontact trench 22 (second trench), an n⁺-type drain region 24, ann⁻-type drift region 26 (first silicon carbide region), a p-type bodyregion 28 (second silicon carbide region), an n⁺-type source region 30(third silicon carbide region), a p⁺-type high concentration region 31(fourth silicon carbide region), a p⁺-type electric field relaxationregion 32 (sixth silicon carbide region), and an n-type high resistanceregion 33 (fifth silicon carbide region).

The silicon carbide layer 10 is located between the source electrode 12and the drain electrode 14. The silicon carbide layer 10 has a firstplane (“P1” in FIG. 1) and a second plane (“P2” in FIG. 1). Hereinafter,the first plane P1 is also referred to as a front surface, and thesecond plane P2 is also referred to as a back surface. The second planeP2 faces the first plane P1.

The first direction and the second direction are directions parallel tothe first plane P1. The second direction is a direction perpendicular tothe first direction. In addition, the third direction is a directionperpendicular to the first plane. The third direction is a directionperpendicular to the first direction and the second direction.

Hereinafter, “depth” denotes a depth based on the first plane P1.

The silicon carbide layer 10 is single crystal SiC. The silicon carbidelayer 10 is, for example, 4H-SiC. The silicon carbide layer 10 has athickness of, for example, 5 μm or more and 500 μm or less.

The first plane P1 is, for example, a plane inclined at 0 degree or moreand 8 degrees or less with respect to the (0001) face. That is, thefirst plane P1 is a plane of which normal line is inclined at 0 degreeor more and 8 degrees or less with respect to the c-axis in the [0001]direction. In other words, the off angle with respect to the (0001) faceis 0 degree or more and 8 degrees or less. In addition, the second planeP2 is, for example, a plane inclined at 0 degree or more and 8 degreesor less with respect to the (000-1) face.

The (0001) face is called a silicon face. The (000-1) face is called acarbon face. The inclination direction of the first plane P1 and thesecond plane P2 is, for example, the [11-20] direction. The [11-20]direction is the a-axis direction. In FIGS. 1 and 2, for example, thefirst direction or the second direction illustrated in the figures isthe a-axis direction.

The gate trench 21 exists in the silicon carbide layer 10. The gatetrench 21 is located on the side of the silicon carbide layer 10 closerto the first plane P1. The gate trench 21 is a groove formed in thesilicon carbide layer 10.

The gate trench 21 extends in the first direction as illustrated in FIG.2. The gate trench 21 has a stripe shape as illustrated in FIG. 2.

The gate trenches 21 are repeatedly arranged in the second direction asillustrated in FIGS. 1 and 2. The depth of the gate trench 21 is, forexample, 1 μm or more and 2 μm or less. The width of the gate trench 21in the second direction is, for example, 0.5 μm or more and 1 μm orless.

The gate trench 21 penetrates the source region 30 and the body region28.

The contact trench 22 exists in the silicon carbide layer 10. Thecontact trench 22 is located on the side of the silicon carbide layer 10closer to the first plane P1. The contact trench 22 is a groove formedin the silicon carbide layer 10.

The contact trench 22 extends in the first direction as illustrated inFIG. 2. The contact trench 22 has a stripe shape as illustrated in FIG.2.

The contact trenches 22 are repeatedly arranged in the second directionas illustrated in FIGS. 1 and 2, and the depth of the contact trench 22is, for example, 1 μm or more and 2 μm or less. The width of the contacttrench 22 in the second direction is, for example, 0.5 μm or more and 1μm or less.

The contact trench 22 penetrates the source region 30 and the bodyregion 28.

The contact trench 22 is provided between the two gate trenches 21. Thewidth of the contact trench 22 in the second direction and the width ofthe gate trench 21 in the second direction are, for example, equal.

The depth of the contact trench 22 and the depth of the gate trench 21are, for example, equal. In other words, the distance from the secondplane P2 to the gate trench 21 is equal to the distance from the secondplane P2 to the contact trench 22.

The gate electrode 16 is located in the gate trench 21. The gateelectrode 16 is provided between the source electrode 12 and the drainelectrode 14. The gate electrode 16 extends in the first direction.

The gate electrode 16 is a conductive layer. The gate electrode 16 is,for example, polycrystalline silicon containing a p-type impurity or ann-type impurity.

The gate insulating layer 18 is located between the gate electrode 16and the silicon carbide layer 10. The gate insulating layer 18 isprovided between the source region 30 and the gate electrode 16, betweenthe body region 28 and the gate electrode 16, and between the driftregion 26 and the gate electrode 16.

The gate insulating layer 18 is, for example, a silicon oxide film. Forexample, a high dielectric constant insulating film can be applied tothe gate insulating layer 18. In addition, for example, a stacked filmof a silicon oxide film and a high dielectric constant insulating filmcan be applied to the gate insulating layer 18.

The interlayer insulating layer 20 is provided on the gate electrode 16.The interlayer insulating layer 20 is provided between the gateelectrode 16 and the source electrode 12.

For example, the thickness of the interlayer insulating layer 20 islarger than the thickness of the gate insulating layer 18. Theinterlayer insulating layer 20 is, for example, a silicon oxide film.The interlayer insulating layer 20 electrically separates the gateelectrode 16 and the source electrode 12.

The source electrode 12 is located on side of the silicon carbide layer10 closer to the first plane P1. The source electrode 12 is provided onthe first plane P1 of the silicon carbide layer 10. The source electrode12 is in contact with the source region 30 and the electric fieldrelaxation region 32.

The source electrode 12 is in contact with the source region 30 on thefirst plane P1 of the silicon carbide layer 10.

The contact region 12 a that is a portion of the source electrode 12 islocated in the contact trench 22. The contact region 12 a is in contactwith the source region 30 on the side surface of the contact trench 22.The contact region 12 a is in contact with the electric field relaxationregion 32 on the side and bottom surfaces of the contact trench 22.

The source electrode 12 contains a metal. The metal forming the sourceelectrode 12 has, for example, a stacked structure of titanium (Ti) andaluminum (Al). The source electrode 12 may contain, for example, metalsilicide or metal carbide in contact with the silicon carbide layer 10.

The drain electrode 14 is located on the side of the silicon carbidelayer 10 closer to the second plane P2. The drain electrode 14 isprovided on the second plane P2 of the silicon carbide layer 10. Thedrain electrode 14 is in contact with the drain region 24.

The drain electrode 14 is, for example, a metal or a metal semiconductorcompound. The drain electrode 14 contains, for example, a materialselected from the group consisting of nickel silicide (NiSi), titanium(Ti), nickel (Ni), silver (Ag), and gold (Au).

The n⁺-type drain region 24 is provided on the side of the siliconcarbide layer 10 closer to the second plane P2. The drain region 24contains, for example, nitrogen (N) as an n-type impurity. The n-typeimpurity concentration of the drain region 24 is, for example, 1×10¹⁸cm⁻³ or more and 1×10²¹ cm⁻³ or less.

The n⁻-type drift region 26 is provided on the drain region 24. Thedrift region 26 is located between the first plane P1 and the drainregion 24.

The drift region 26 contains, for example, nitrogen (N) as an n-typeimpurity. The n-type impurity concentration of the drift region 26 islower than the n-type impurity concentration of the drain region 24. Then-type impurity concentration of the drift region 26 is, for example,4×10¹⁴ cm⁻³ or more and 1×10¹⁸ cm⁻³ or less.

The p-type body region 28 is located between the drift region 26 and thefirst plane P1. The body region 28 is located between the gate trench 21and the contact trench 22.

The body region 28 functions as a channel formation region of the MOSFET100. For example, during the time of on-operation of the MOSFET 100, achannel through which electrons flow is formed in a region of the bodyregion 28 in contact with the gate insulating layer 18. The region ofthe body region 28 in contact with the gate insulating layer 18 becomesa channel formation region.

The body region 28 contains, for example, aluminum (Al) as a p-typeimpurity. The p-type impurity concentration of the body region 28 is,for example, 5×10¹⁶ cm⁻³ or more and 5×10¹′ cm⁻³ or less.

The depth of the body region 28 is smaller than the depth of the gatetrench 21. The depth of the body region 28 is, for example, 0.4 μm ormore and 1.0 μm or less.

The thickness of the body region 28 in the depth direction (thirddirection) is, for example, 0.1 μm or more and 0.3 μm or less.

The n⁺-type source region 30 is located between the body region 28 andthe first plane P1. The source region 30 is located between the gatetrench 21 and the contact trench 22.

The source region 30 is in contact with the source electrode 12. Thesource region 30 is in contact with the gate insulating layer 18.

The source region 30 contains, for example, phosphorus (P) as an n-typeimpurity. The source region 30 has an n-type impurity concentrationhigher than the drift region 26. The n-type impurity concentration ofthe source region 30 is, for example, 1×10¹⁹ cm⁻³ or more and 1×10²¹cm⁻³ or less.

The depth of the source region 30 is smaller than the depth of the bodyregion 28. The depth of the source region 30 is, for example, 0.1 μm ormore and 0.4 μm or less.

The p⁺-type electric field relaxation region 32 is located between thecontact trench 22 and the drift region 26. The electric field relaxationregion 32 is in contact with the bottom surface of the contact trench22. The electric field relaxation region 32 is in contact with thecontact region 12 a of the source electrode 12.

The electric field relaxation region 32 is located between the contacttrench 22 and the body region 28. The electric field relaxation region32 is in contact with the side surface of the contact trench 22.

The electric field relaxation region 32 has a function of relaxing theelectric field applied to the gate insulating layer 18 at the time ofoff-operation of the MOSFET 100. The electric field relaxation region 32is fixed at, for example, the same potential as the source electrode 12.

The electric field relaxation region 32 contains, for example, aluminum(Al) as a p-type impurity. The p-type impurity concentration of theelectric field relaxation region 32 is higher than the p-type impurityconcentration of the body region 28. The p-type impurity concentrationof the electric field relaxation region 32 is, for example, ten times ormore of the p-type impurity concentration of the body region 28. Thep-type impurity concentration of the electric field relaxation region 32is, for example, 5×10¹⁷ cm⁻³ or more and 5×10²⁰ cm⁻³ or less.

The p⁺-type high concentration region 31 is located between the driftregion 26 and the first plane P1. At least a portion of the highconcentration region 31 is located in the body region 28. The highconcentration region 31 is located between gate trench 21 and thecontact trench 22.

A portion of the body region 28 is located between the gate insulatinglayer 18 and the high concentration region 31. The high concentrationregion 31 is not in contact with, for example, the gate insulating layer18. The high concentration region 31 is provided, for example, at aposition away from the gate insulating layer 18 in the second direction.

The p⁺-type high concentration region 31 has, for example, a function ofsuppressing the short channel effect of the MOSFET 100. The highconcentration region 31 has, for example, a function of suppressing adecrease in breakdown voltage of the MOSFET 100.

The high concentration region 31 contains, for example, aluminum (Al) asa p-type impurity. The p-type impurity concentration of the highconcentration region 31 is higher than the p-type impurity concentrationof the body region 28. The p-type impurity concentration of the highconcentration region 31 is, for example, 1×10¹⁶ cm⁻³ or more and 5×10¹⁹cm⁻³ or less.

As illustrated in FIG. 3, a first position (X in FIG. 3) and a secondposition (Y in FIG. 3) exist in the high concentration region 31 in thebody region 28. A first distance (d1 in FIG. 3) from the first plane P1to the first position X is smaller than a second distance (d2 in FIG. 3)from the first plane P1 to the second position Y, and a third distance(d3 in FIG. 3) from the gate insulating layer 18 to the first position Xis smaller than a fourth distance (d4 in FIG. 3) from the gateinsulating layer 18 to the second position Y. The high concentrationregion 31 becomes deeper from the gate trench 21 toward the contacttrench 22 in the body region 28.

FIG. 4 is a view illustrating an impurity concentration distribution ofthe semiconductor device according to the first embodiment. FIG. 4illustrates the concentration distribution of the p-type impurity in thebody region 28 in the second direction.

As illustrated in FIG. 4, the first concentration distribution of thep-type impurity on the first virtual line including the first position Xof the high concentration region 31 and extending in the seconddirection has a first concentration peak at the first position X. Inaddition, as illustrated in FIG. 4, the second concentrationdistribution of the p-type impurity on the second virtual line includingthe second position Y and extending in the second direction has a secondconcentration peak at the second position Y.

In addition, on the first virtual line and the second virtual line,other concentration peaks different from the first concentration peakand the second concentration peak also exist in the electric fieldrelaxation region 32 between the gate trench 21 and the contact trench22, respectively.

The angle (θ in FIG. 3) of the segment (L in FIG. 3) connecting thefirst position X and the second position Y with respect to the normalline (dotted line in FIG. 3) of the first plane P1 is 20 degrees or moreand 50 degrees or less. In other words, the high concentration region 31is inclined from 20 degrees or more to 50 degrees or less with respectto the third direction.

The inclination of the high concentration region 31 in the thirddirection is larger than the inclination of the side surface of thecontact trench 22 in the third direction.

The third distance d3 is, for example, 0.05 μm or more and 0.4 μm orless, and the fourth distance d4 is, for example, 0.1 μm or more and 0.5μm or less. The third distance d3 is, for example, half or less of thedistance (d5 in FIG. 3) between the gate insulating layer 18 and thecontact trench 22.

The p-type impurity concentration at the first position X and the p-typeimpurity concentration at the second position Y are, for example, 2times or more and 100 times or less of the p-type impurity concentrationnear the gate insulating layer 18 (for example, the position Z in FIG.3) in the body region 28. The vicinity of the gate insulating layer 18in the body region 28 is, for example, a position less than 0.05 μm fromthe gate insulating layer 18.

The high concentration region 31 is in contact with, for example, thedrift region 26. A portion of the high concentration region 31 islocated, for example, in the drift region 26.

The high concentration region 31 is in contact with, for example, theelectric field relaxation region 32.

The high concentration region 31 is in contact with, for example, thesource region 30.

The n-type high resistance region 33 is located in the source region 30.The high resistance region 33 is located between the high concentrationregion 31 and the first plane P1.

The high resistance region 33 has, for example, a function of improvingthe short-circuit withstand capability of the MOSFET 100.

The high resistance region 33 contains, for example, phosphorus (P) asan n-type impurity. The n-type impurity concentration of the highresistance region 33 is lower than the n-type impurity concentration ofthe source region 30. The n-type impurity concentration of the highresistance region 33 is, for example, 1×10¹⁸ cm⁻³ or more and 1×10²⁰cm⁻³ or less.

The high resistance region 33 is in contact with, for example, the firstplane P1. The high resistance region 33 is in contact with, for example,the high concentration region 31.

Next, an example of the method of manufacturing the semiconductor deviceaccording to the first embodiment will be described.

A method of manufacturing the semiconductor device according to thefirst embodiment includes: forming a second silicon carbide region ofp-type on a side of a first plane of a silicon carbide layer, thesilicon carbide layer having a first plane, a second plane facing thefirst plane, and a first silicon carbide region of n-type locatedbetween the second plane and the first plane; forming a third siliconcarbide region of n-type between the second silicon carbide region andthe first plane; forming a mask material having an opening on aside ofthe first plane of the silicon carbide layer; forming a fourth siliconcarbide region of p-type by ion-implanting p-type impurities into thesilicon carbide layer in a direction inclined at a first angle withrespect to a normal line of the first plane by using the mask materialas a mask, at least a portion of the fourth silicon carbide region beinglocated in the second silicon carbide region; forming a first trench onaside of the first plane of the silicon carbide layer; forming a gateinsulating layer in the first trench; and forming a gate electrode onthe gate insulating layer in the first trench. A first position and asecond position exist in the at least a portion of the fourth siliconcarbide region, a first distance from the first plane to the firstposition is smaller than a second distance from the first plane to thesecond position, and a third distance from the gate insulating layer tothe first position is smaller than a fourth distance from the gateinsulating layer to the second position.

FIGS. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and 19 areschematic cross-sectional views illustrating an example of the method ofmanufacturing the semiconductor device according to the firstembodiment. FIGS. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, and19 illustrate cross-sections corresponding to FIG. 1.

First, a silicon carbide layer 10 having an n⁺-type drain region 24 andan n⁻-type epitaxial layer 11 formed on the drain region 24 by epitaxialgrowth is prepared (FIG. 5). A portion of the epitaxial layer 11eventually becomes the drift region 26.

The silicon carbide layer 10 has a first plane (“P1” in FIG. 5) and asecond plane (“P2” in FIG. 5). Hereinafter, the first plane P1 is alsoreferred to as a front surface, and the second plane P2 is also referredto as a back surface.

Next, a p-type body region 28 is formed in the epitaxial layer 11 by anion implantation method (FIG. 6).

Next, an n⁺-type source region 30 is formed in the epitaxial layer 11 byan ion implantation method (FIG. 7). The source region 30 is formedbetween the body region 28 and the first plane P1.

Next, a mask material 50 is formed on the front surface of the siliconcarbide layer 10 (FIG. 8). The mask material 50 has an opening 70. Themask material 50 is formed, for example, by depositing a film by achemical vapor deposition method (CVD method) and patterning the film byusing a lithography method and a reactive ion etching method (RIEmethod). The mask material 50 is, for example, a silicon oxide film.

Next, a gate trench 21 (first trench) and a contact trench 22 (secondtrench) are formed by using the mask material 50 as a mask (FIG. 9). Thegate trench 21 and the contact trench 22 are formed by using an RIEmethod. The gate trench 21 and the contact trench 22 are formed so as topenetrate the source region 30 and the body region 28. The contacttrench 22 is formed in the silicon carbide layer 10 below the opening 70of the mask material 50.

Next, a mask material 52 is formed on the silicon carbide layer 10 (FIG.10). The mask material 52 covers the mask material 50 and the gatetrench 21. The mask material 52 is, for example, a photoresist.

Next, a p⁺-type electric field relaxation region 32 is formed (FIG. 11).The electric field relaxation region 32 is formed by implanting p-typeimpurities into the contact trench 22 by oblique ion implantation methodby using the mask material 52 and the mask material 50 as a mask. Thep-type impurity is, for example, an aluminum ion. Aluminum ions areion-implanted in a direction inclined at a second angle (02 in FIG. 11)with respect to a normal line (dotted line in FIG. 11) of the firstplane P1. The p⁺-type electric field relaxation region 32 is formed nearthe side and bottom surfaces of the contact trench 22 in the siliconcarbide layer 10.

Next, a p⁺-type high concentration region 31 is formed (FIG. 12). Thehigh concentration region 31 is formed by implanting p-type impuritiesinto the contact trench 22 by oblique ion implantation method by usingthe mask material 52 and the mask material 50 as a mask. The p-typeimpurity is, for example, an aluminum ion. Aluminum ions areion-implanted in a direction inclined at a first angle (θ1 in FIG. 12)with respect to a normal line (dotted line in FIG. 12) of the firstplane P1.

The first angle θ1 is larger than the second angle θ2. In other words,the second angle θ2 is smaller than the first angle θ1.

A portion of the p-type impurities ion-implanted into the contact trench22 is implanted into the side surface of the contact trench 22 afterlosing kinetic energy due to passing through the mask material 52 andthe mask material 50. Therefore, the depth of the high concentrationregion 31 increases from the gate trench 21 toward the contact trench22.

An n-type high resistance region 33 is formed simultaneously with thehigh concentration region 31. The high resistance region 33 is formed inthe source region 30. By introducing the p-type impurities into thesource region 30, the n-type impurity concentration is reduced, andthus, the high resistance region 33 with a low n-type impurityconcentration is formed.

Next, the mask material 52 and the mask material 50 are peeled off (FIG.13). Next, activation annealing of an n-type impurity and a p-typeimpurity is performed.

Next, a first silicon oxide film 60 and a polycrystalline silicon film61 are formed in the gate trench 21 and the contact trench 22 (FIG. 14).

The first silicon oxide film 60 and the polycrystalline silicon film 61are formed by, for example, a CVD method. A portion of the first siliconoxide film 60 becomes the gate insulating layer 18. A portion of thepolycrystalline silicon film 61 becomes the gate electrode 16.

Next, the polycrystalline silicon film 61 on the front surface of thesilicon carbide layer 10 is removed (FIG. 15). The polycrystallinesilicon film 61 on the front surface of the silicon carbide layer 10 isremoved by, for example, a dry etching method. A portion of thepolycrystalline silicon film 61 remains in the gate trench 21 and thecontact trench 22.

Next, a mask material 54 is formed on the front surface of the siliconcarbide layer 10. The mask material 54 is, for example, a photoresist.

The mask material 54 covers the gate trench 21. The mask material 54covers the polycrystalline silicon film 61 in the gate trench 21.

Next, the polycrystalline silicon film 61 in the contact trench 22 isremoved by using the mask material 54 as a mask (FIG. 16). Thepolycrystalline silicon film 61 is removed by, for example, a dryetching method.

Next, the mask material 54 is removed. Next, a second silicon oxide film62 is formed on the first silicon oxide film 60 and the polycrystallinesilicon film 61 (FIG. 17). The second silicon oxide film 62 is formedby, for example, a CVD method. A portion of the second silicon oxidefilm 62 becomes the interlayer insulating layer 20.

Next, a mask material 56 is formed on the second silicon oxide film 62.The mask material 56 is, for example, a photoresist.

Next, the first silicon oxide film 60 and the second silicon oxide film62 in the contact trench 22 are removed by using the mask material 56 asa mask (FIG. 18). The first silicon oxide film 60 and the second siliconoxide film 62 are removed by, for example, a wet etching method.

Next, the mask material 56 is removed. Next, a source electrode 12 isformed in the contact trench 22 and on the second silicon oxide film 62(FIG. 19). The source electrode 12 is formed, for example, by depositinga metal film by a CVD method.

After that, the drain electrode 14 is formed on the back surface of thesilicon carbide layer 10 by using a known process technique.

A first position X and a second position Y exist in the highconcentration region 31 in the body region 28 manufactured by the abovemanufacturing method. The first distance d1 from the first plane P1 tothe first position X is smaller than the second distance d2 from thefirst plane P1 to the second position Y, and the third distance d3 fromthe gate insulating layer 18 to the first position X is smaller than thefourth distance d4 from the gate insulating layer 18 to the secondposition Y. The high concentration region 31 becomes deeper from thegate trench 21 toward the contact trench 22 in the body region 28.

By the above manufacturing method, the MOSFET 100 illustrated in FIGS. 1to 3 is manufactured.

Next, the functions and effects of the semiconductor device according tothe first embodiment and the method of manufacturing the semiconductordevice will be described.

A trench gate structure in which the gate electrode 16 is provided inthe gate trench 21 is applied to the MOSFET 100. By applying the trenchgate structure, the channel area per unit area increased, and theon-resistance of the MOSFET 100 is reduced.

In addition, in the MOSFET 100, a contact region 12 a that is a portionof the source electrode 12 is provided in the contact trench 22. TheMOSFET 100 is a MOSFET having a so-called double trench structure.

By providing the contact region 12 a in the contact trench 22,electrical connection to the body region 28 and the source region 30 canbe acquired on the side surface of the contact trench 22. Therefore, thecontact area of the source electrode 12 on the front surface of thesilicon carbide layer 10 can be reduced. Therefore, the channel area perunit area increases, and the on-resistance of the MOSFET 100 decreases.

The MOSFET 100 includes the electric field relaxation region 32 aroundthe bottom and side surfaces of the contact trench 22. Therefore, duringthe time of off-operation of the MOSFET 100, the electric field appliedto the gate insulating layer 18 is relaxed. Therefore, the reliabilityof the gate insulating layer 18 is improved.

FIG. 20 is a schematic cross-sectional view of a semiconductor deviceaccording to Comparative Example. The semiconductor device according toComparative Example is a MOSFET 900 having a double trench structure.

The MOSFET 900 of Comparative Example is different from the MOSFET 100according to the first embodiment in that the silicon carbide layer 10does not have the p⁺-type high concentration region 31 and the n-typehigh resistance region 33.

In the MOSFET 900, for example, if the thickness of the p-type bodyregion 28 in the third direction can be reduced, the channel length ofthe MOSFET 900 can be shortened, and thus, the on-resistance can bereduced. However, if the thickness of the body region 28 in the thirddirection is reduced, there is concern that the threshold voltage of theMOSFET 900 decreases due to an electric field extending from the side ofthe drift region 26 to the body region 28. That is, the so-called shortchannel effect may become apparent.

If the thickness of the body region 28 in the third direction isreduced, punch-through occurs between the source region 30 and the driftregion 26 at the time of turning off the MOSFET 900, and there isconcern that the breakdown voltage of the MOSFET 100 is reduced.

The MOSFET 100 according to the first embodiment has a p⁺-type highconcentration region 31 in the body region 28. The high concentrationregion 31 is provided at a position away from the gate insulating layer18 in the second direction.

The high concentration region 31 is provided at a position away from thegate insulating layer 18 and the channel formation region by a certaindistance in the body region 28, so that the extension of the electricfield extending from the side of the drift region 26 to the body region28 is suppressed. Therefore, the short channel effect is suppressed.Therefore, the thickness of the p-type body region 28 in the thirddirection can be reduced, and the on-resistance can be reduced.

The high concentration region 31 is provided at a position away from thegate insulating layer 18 in the second direction. Therefore, thefluctuation of the threshold value of the MOSFET 100 caused by providingthe high concentration region 31 is suppressed.

In addition, according to the manufacturing method according to thefirst embodiment, when the high concentration region 31 is formed, thep-type impurities are ion-implanted into the body region 28 from theside of the contact trench 22. Therefore, the p-type impurities do notpass through the channel formation region on the side of the gate trench21 during the time of ion implantation. Therefore, defects due to ionimplantation damage do not occur in the channel formation region.Therefore, a decrease in carrier mobility due to defects is suppressed.

From the viewpoint of suppressing fluctuation of the threshold value ofthe MOSFET 100 caused by providing the high concentration region 31, thethird distance d3 between the gate insulating layer 18 and the positionX of the high concentration region 31 is preferably 0.05 μm or more,more preferably 0.1 μm or more.

In addition, from the viewpoint of suppressing the short channel effect,the third distance d3 between the gate insulating layer 18 and theposition X of the high concentration region 31 is preferably a half orless, more preferably one-third or less of the distance (d5 in FIG. 3)between the gate insulating layer 18 and the contact trench 22. Inaddition, from the viewpoint of suppressing the short channel effect,the fourth distance d4 between the gate insulating layer 18 and theposition Y of the high concentration region 31 is preferably 0.5 μm orless.

In addition, from the viewpoint of suppressing the short channel effect,it is preferable that the angle (θ in FIG. 3) of the segment (L in FIG.3) connecting the first position X and the second position Y withrespect to the normal line (dotted line in FIG. 3) of the first plane P1is 50 degrees or less.

The high concentration region 31 becomes deeper from the gate trench 21toward the contact trench 22 in the body region 28. In other words, ahigh concentration region 31 having a high p-type impurity concentrationalso exists in a portion of the body region 28 closer to the contacttrench 22.

Since the high concentration region 31 having a high p-type impurityconcentration also exists in a portion of the body region 28 closer tothe contact trench 22, even in a case where the thickness of the p-typebody region 28 in the third direction is reduced, punch-through betweenthe source region 30 and the drift region 26 is suppressed. Therefore, adecrease in breakdown voltage of the MOSFET 100 is suppressed.

From the viewpoint of suppressing punch-through between the sourceregion 30 and the drift region 26, it is preferable that the highconcentration region 31 is in contact with the electric field relaxationregion 32.

From the viewpoint of suppressing punch-through between the sourceregion 30 and the drift region 26, it is preferable that the angle (θ inFIG. 3) of the segment (L in FIG. 3) connecting the first position X andthe second position Y with respect to the normal line (dotted line inFIG. 3) of the first plane P1 is 20 degrees or more.

From the viewpoint of suppressing the short channel effect and theviewpoint of suppressing punch-through, the p-type impurityconcentration at the first position X and the p-type impurityconcentration at the second position Y are preferably 2 times or more,more preferably 5 times or more, further preferably 10 times or more ofthe p-type impurity concentration near the gate insulating layer 18 (forexample, the position Z in FIG. 3) of the body region 28.

For example, in a case where a short circuit occurs in the loadconnected to the MOSFET 100 during the time of on-operation of theMOSFET 100, a large current flows through the MOSFET 100. If the currentflowing during the time of the short circuit of the load increases, thetime taken for the MOSFET 100 to be destroyed decreases. That is, theshort-circuit withstand capability decreases.

The MOSFET 100 according to the first embodiment has an n-type highresistance region 33 in the source region 30. Therefore, in a case wherea short circuit occurs in the load connected to the MOSFET 100, thecurrent flowing through the MOSFET 100 can be reduced. Therefore, theshort-circuit withstand capability of the MOSFET 100 is improved.

From the viewpoint of improving the short-circuit withstand capabilityof the MOSFET 100, it is preferable that the high resistance region 33is in contact with the first plane P1. In addition, it is preferablethat the high resistance region 33 is in contact with the highconcentration region 31.

As described above, according to the first embodiment, it is possible torealize a MOSFET capable of reducing the on-resistance. In addition, itis possible to realize a MOSFET capable of suppressing a decrease inbreakdown voltage. In addition, it is possible to realize a MOSFETcapable of improving the short-circuit withstand capability.

Second Embodiment

A method of manufacturing a semiconductor device according to a secondembodiment is different from the method of manufacturing thesemiconductor device according to the first embodiment in that the firsttrench is formed after forming the fourth silicon carbide region.Hereinafter, a portion of contents overlapping with the semiconductordevice according to the first embodiment may be omitted in description.

Hereinafter, an example of the method of manufacturing the semiconductordevice according to the second embodiment will be described. The methodof manufacturing a semiconductor device according to the secondembodiment is the method of manufacturing the MOSFET 100 according tothe first embodiment.

FIGS. 21, 22, 23, and 24 are schematic cross-sectional viewsillustrating an example of the method of manufacturing the semiconductordevice according to the second embodiment. FIGS. 21, 22, 23, and 24illustrate cross sections corresponding to FIG. 1.

The processes up to the formation of the n⁺-type source region 30 arethe same as those in the method of manufacturing the semiconductordevice according to the first embodiment.

Next, a mask material 50 is formed on the front surface of the siliconcarbide layer 10 (FIG. 20). The mask material 50 has an opening 70.

Next, a contact trench 22 (second trench) is formed by using the maskmaterial 50 as a mask (FIG. 21). The contact trench 22 is formed in thesilicon carbide layer 10 below the opening 70 of the mask material 50.

Next, a p⁺-type electric field relaxation region 32 is formed (FIG. 22).The electric field relaxation region 32 is formed by implanting p-typeimpurities into the contact trench 22 by oblique ion implantation methodby using the mask material 52 and the mask material 50 as a mask. Thep-type impurity is, for example, an aluminum ion. Aluminum ions areion-implanted in a direction inclined at a second angle (02 in FIG. 22)with respect to a normal line (dotted line in FIG. 22) of the firstplane P1. The p⁺-type electric field relaxation region 32 is formed nearthe side and bottom surfaces of the contact trench 22 in the siliconcarbide layer 10.

Next, a p⁺-type high concentration region 31 is formed (FIG. 23). Thehigh concentration region 31 is formed by implanting p-type impuritiesinto the contact trench 22 by oblique ion implantation method by usingthe mask material 52 and the mask material 50 as a mask. The p-typeimpurities are aluminum ions. Aluminum ions are ion-implanted in adirection inclined at a first angle (θ1 in FIG. 23) with respect to anormal line (dotted line in FIG. 23) of the first plane P1.

The first angle θ1 is larger than the second angle θ2. In other words,the second angle θ2 is smaller than the first angle θ1.

Next, the mask material 51 is peeled off. Next, a mask material 53 isformed. The mask material 53 is, for example, a silicon oxide film. Themask material 53 covers the contact trench 22.

Next, a gate trench 21 (first trench) is formed by using the maskmaterial 53 as a mask (FIG. 24).

Next, the mask material 53 is peeled off. After that, the MOSFET 100illustrated in FIGS. 1 to 3 is manufactured by the same manufacturingmethod as the method of manufacturing the semiconductor device accordingto the first embodiment.

A first position X and a second position Y exist in the highconcentration region 31 in the body region 28 manufactured by the methodof manufacturing the semiconductor device according to the secondembodiment. A first distance d1 from the first plane P1 to the firstposition X is smaller than a second distance d2 from the first plane P1to the second position Y, and a third distance d3 from the gateinsulating layer 18 to the first position X is smaller than a fourthdistance d4 from the gate insulating layer 18 to the second position Y.The high concentration region 31 becomes deeper from the gate trench 21toward the contact trench 22 in the body region 28.

In the method of manufacturing the semiconductor device according to thesecond embodiment, unlike the method of manufacturing the semiconductordevice according to the first embodiment, the gate trench 21 and thecontact trench 22 can be formed independently. Therefore, for example,the contact trench 22 having a depth or a taper angle of the sidesurface different from that of the gate trench 21 can be easily formed.

As described above, according to the second embodiment, it is possibleto realize a MOSFET capable of reducing the on-resistance. In addition,it is possible to realize a MOSFET capable of suppressing a decrease inbreakdown voltage. In addition, it is possible to realize a MOSFETcapable of improving the short-circuit withstand capability.

Third Embodiment

A semiconductor device according to a third embodiment is different fromthe semiconductor device according to the first embodiment in that thesilicon carbide layer does not have a second trench. Hereinafter, aportion of contents overlapping with the semiconductor device accordingto the first embodiment may be omitted in description.

FIG. 25 is a schematic cross-sectional view of the semiconductor deviceaccording to the third embodiment. FIG. 25 is a view corresponding toFIG. 1 of the first embodiment.

The semiconductor device according to the third embodiment includes asilicon carbide layer 10, a source electrode 12 (first electrode), adrain electrode 14 (second electrode), a gate electrode 16, a gateinsulating layer 18, and an interlayer insulating layer 20.

The silicon carbide layer 10 includes a gate trench 21 (first trench),an n⁺-type drain region 24, an n⁻-type drift region 26 (first siliconcarbide region), and a p-type body region 28 (second silicon carbideregion), an n⁺-type source region 30 (third silicon carbide region), ap⁺-type high concentration region 31 (fourth silicon carbide region), ann-type high resistance region 33 (fifth silicon carbide region), and ap⁺-type contact 40.

The silicon carbide layer 10 does not include a contact trench. Thesource electrode 12 is in contact with the p⁺-type contact 40 on thefirst plane P1.

FIGS. 26 and 27 are schematic cross-sectional views illustrating anexample of a method of manufacturing a semiconductor device according tothe third embodiment. FIGS. 26 and 27 illustrate cross-sectionscorresponding to FIG. 25.

The processes up to the formation of the n⁺-type source region 30 arethe same as those in the method of manufacturing the semiconductordevice according to the first embodiment.

Next, a mask material 50 is formed on the front surface of the siliconcarbide layer 10 (FIG. 26). The mask material 50 has an opening 70.

Next, a p⁺-type high concentration region 31 is formed (FIG. 27). Thehigh concentration region 31 is formed by implanting p-type impuritiesinto the silicon carbide layer 10 by oblique ion implantation methodusing the mask material 50 as a mask. The p-type impurities are, forexample, aluminum ions. Aluminum ions are ion-implanted in a directioninclined at a first angle (θ1 in FIG. 27) with respect to a normal line(dotted line in FIG. 27) of the first plane P1.

After that, using the same processes technology as those of the methodof manufacturing the semiconductor device according to the firstembodiment, a p⁺-type contact 40, a gate trench 21 (first trench), asource electrode 12 (first electrode), a drain electrode 14 (secondelectrode), a gate electrode 16, a gate insulating layer 18, and aninterlayer insulating layer 20 are formed. With the above manufacturingmethod, the MOSFET 200 illustrated in FIG. 25 is manufactured.

As described above, according to the third embodiment, it is possible torealize a MOSFET that can reduce the on-resistance. In addition, it ispossible to realize a MOSFET capable of suppressing a decrease inbreakdown voltage. In addition, it is possible to realize a MOSFETcapable of improving short-circuit withstand capability.

Fourth Embodiment

An inverter circuit and a driving device according to a fourthembodiment are driving devices including the semiconductor deviceaccording to the first embodiment.

FIG. 28 is a schematic view of the driving device according to thefourth embodiment. The driving device 1000 includes a motor 140 and aninverter circuit 150.

The inverter circuit 150 is configured with three semiconductor modules150 a, 150 b, and 150 c using the MOSFET 100 according to the firstembodiment as a switching element. By connecting the three semiconductormodules 150 a, 150 b, 150 c in parallel, a three-phase inverter circuit150 having three AC voltage output terminals U, V, and W is realized.The motor 140 is driven by the AC voltage output from the invertercircuit 150.

According to the fourth embodiment, by providing the MOSFET 100 withimproved characteristics, the characteristics of the inverter circuit150 and the driving device 1000 are improved.

Fifth Embodiment

A vehicle according to a fifth embodiment is a vehicle including thesemiconductor device according to the first embodiment.

FIG. 29 is a schematic view of a vehicle according to the fifthembodiment. The vehicle 1100 according to the fifth embodiment is arailway vehicle. The vehicle 1100 includes a motor 140 and an invertercircuit 150.

The inverter circuit 150 is configured with three semiconductor modulesusing the MOSFET 100 according to the first embodiment as a switchingelement. By connecting three semiconductor modules in parallel, athree-phase inverter circuit 150 having three AC voltage outputterminals U, V, and W is realized. The motor 140 is driven by the ACvoltage output from the inverter circuit 150. The wheels 90 of thevehicle 1100 are rotated by the motor 140.

According to the fifth embodiment, by providing the MOSFET 100 withimproved characteristics, the characteristics of the vehicle 1100 areimproved.

Sixth Embodiment

A vehicle according to a sixth embodiment is a vehicle including thesemiconductor device according to the first embodiment.

FIG. 30 is a schematic view of a vehicle according to the sixthembodiment. The vehicle 1200 according to the sixth embodiment is anautomobile. The vehicle 1200 includes a motor 140 and an invertercircuit 150.

The inverter circuit 150 is configured with three semiconductor modulesusing the MOSFET 100 according to the first embodiment as a switchingelement. By connecting three semiconductor modules in parallel, athree-phase inverter circuit 150 having three AC voltage outputterminals U, V, and

W is realized.

The motor 141 is driven by the AC voltage output from the invertercircuit 150. The wheels 90 of the vehicle 1200 are rotated by the motor140.

According to the sixth embodiment, by providing the MOSFET 100 withimproved characteristics, the characteristics of the vehicle 1200 areimproved.

Seventh Embodiment

An elevator according to a seventh embodiment is an elevator includingthe semiconductor device according to the first embodiment.

FIG. 31 is a schematic view of an elevator (lift) according to theseventh embodiment. The elevator 1300 according to the seventhembodiment includes a basket 610, a counterweight 612, a wire rope 614,a hoist 616, a motor 140, and an inverter circuit 150.

The inverter circuit 150 is configured with three semiconductor modulesusing the MOSFET 100 according to the first embodiment as a switchingelement. By connecting three semiconductor modules in parallel, athree-phase inverter circuit 150 having three AC voltage outputterminals U, V, and W is realized.

The motor 140 is driven by the AC voltage output from the invertercircuit 150. The hoist 616 is rotated by the motor 140, and the basket610 is raised and lowered.

According to the seventh embodiment, by providing the MOSFET 100 withimproved characteristics, the characteristics of the elevator 1300 areimproved.

As described above, in the first to third embodiments, a case where thecrystal structure of silicon carbide is 4H-SiC has been described as anexample, but the embodiments can be applied to silicon carbides withother crystal structures such as 6H-SiC and 3C-SiC.

In addition, in the fourth to seventh embodiments, a case where thesemiconductor device according to the first embodiment is provided hasbeen described as an example, but the semiconductor device according tothe third embodiment can be applied.

In addition, in the fourth to seventh embodiments, a case where thesemiconductor device according to the embodiments is applied to avehicle or an elevator has been described as an example, but thesemiconductor device according to the embodiments can be applied to, forexample, a power conditioner or the like of a solar power generationsystem.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, semiconductor devices, methods ofmanufacturing a semiconductor device, inverter circuits, drivingdevices, vehicles, and elevators described herein may be embodied in avariety of other forms; furthermore, various omissions, substitutionsand changes in the form of the devices and methods described herein maybe made without departing from the spirit of the inventions. Theaccompanying claims and their equivalents are intended to cover suchforms or modifications as would fall within the scope and spirit of theinventions.

What is claimed is:
 1. A semiconductor device comprising: a siliconcarbide layer having a first plane parallel to a first direction and asecond direction perpendicular to the first direction and a second planefacing the first plane, the silicon carbide layer having a first trenchbeing located on a side of the first plane and extending in the firstdirection, a first silicon carbide region of n-type, a second siliconcarbide region of p-type being located between the first silicon carbideregion and the first plane, a third silicon carbide region of n-typebeing located between the second silicon carbide region and the firstplane, and a fourth silicon carbide region of p-type being locatedbetween the first silicon carbide region and the first plane, at least aportion of the fourth silicon carbide region being located in the secondsilicon carbide region, the fourth silicon carbide region having ahigher p-type impurity concentration than a p-type impurityconcentration of the second silicon carbide region; a gate electrodebeing located in the first trench; a gate insulating layer being locatedbetween the gate electrode and the silicon carbide layer; a firstelectrode being located on a side of the first plane of the siliconcarbide layer; and a second electrode being located on a side of thesecond plane of the silicon carbide layer, wherein a first position anda second position exist in the at least portion of the fourth siliconcarbide region, a first distance from the first plane to the firstposition is smaller than a second distance from the first plane to thesecond position, and a third distance from the gate insulating layer tothe first position is smaller than a fourth distance from the gateinsulating layer to the second position.
 2. The semiconductor deviceaccording to claim 1, wherein the first concentration distribution ofthe p-type impurity on a first virtual line including the first positionand extending in the second direction has a first concentration peak atthe first position, and the second concentration distribution of thep-type impurity on a second virtual line including the second positionand extending in the second direction has a second concentration peak atthe second position.
 3. The semiconductor device according to claim 1,wherein an angle of a segment connecting the first position and thesecond position with respect to a normal line of the first plane is 20degrees or more and 50 degrees or less.
 4. The semiconductor deviceaccording to claim 1, wherein the second silicon carbide region islocated between the gate insulating layer and the fourth silicon carbideregion.
 5. The semiconductor device according to claim 1, wherein thethird distance is 0.05 μm or more, and the fourth distance is 0.5 μm orless.
 6. The semiconductor device according to claim 1, wherein thep-type impurity concentration at the first position and the p-typeimpurity concentration at the second position are 2 times or more and100 times or less of the p-type impurity concentration of the secondsilicon carbide region near the gate insulating layer.
 7. Thesemiconductor device according to claim 1, wherein the fourth siliconcarbide region is in contact with the third silicon carbide region. 8.The semiconductor device according to claim 7, wherein the siliconcarbide layer further includes a fifth silicon carbide region of n-typebeing located in the third silicon carbide region, the fifth siliconcarbide region being located between the fourth silicon carbide regionand the first plane, and the fifth silicon carbide region having ann-type impurity concentration lower than an n-type impurityconcentration of the third silicon carbide region.
 9. The semiconductordevice according to claim 1, wherein the fourth silicon carbide regionis in contact with the first silicon carbide region.
 10. Thesemiconductor device according to claim 1, further comprising a secondtrench being located on a side of the first plane and extending in thefirst direction, wherein a portion of the first electrode is located inthe second trench, and the fourth silicon carbide region is locatedbetween the first trench and the second trench.
 11. The semiconductordevice according to claim 10, wherein the third distance is a half orless of a distance between the gate insulating layer and the secondtrench.
 12. The semiconductor device according to claim 10, wherein thesilicon carbide layer further includes a sixth silicon carbide region ofp-type being located between the second trench and the first siliconcarbide region, and having a p-type impurity concentration higher than ap-type impurity concentration of the second silicon carbide region. 13.The semiconductor device according to claim 12, wherein the fourthsilicon carbide region is in contact with the sixth silicon carbideregion.
 14. An inverter circuit comprising the semiconductor deviceaccording to claim
 1. 15. A driving device comprising the semiconductordevice according to claim
 1. 16. A vehicle comprising the semiconductordevice according to claim
 1. 17. An elevator comprising thesemiconductor device according to claim
 1. 18. A method of manufacturinga semiconductor device comprising: forming a second silicon carbideregion of p-type on a side of a first plane of a silicon carbide layer,the silicon carbide layer having a first plane, a second plane facingthe first plane, and a first silicon carbide region of n-type locatedbetween the second plane and the first plane; forming a third siliconcarbide region of n-type between the second silicon carbide region andthe first plane; forming a mask material having an opening on a side ofthe first plane of the silicon carbide layer; forming a fourth siliconcarbide region of p-type by ion-implanting p-type impurities into thesilicon carbide layer in a direction inclined at a first angle withrespect to a normal line of the first plane by using the mask materialas a mask, at least a portion of the fourth silicon carbide region beinglocated in the second silicon carbide region; forming a first trench ona side of the first plane of the silicon carbide layer; forming a gateinsulating layer in the first trench; and forming a gate electrode onthe gate insulating layer in the first trench, wherein a first positionand a second position exist in the at least a portion of the fourthsilicon carbide region, a first distance from the first plane to thefirst position is smaller than a second distance from the first plane tothe second position, and a third distance from the gate insulating layerto the first position is smaller than a fourth distance from the gateinsulating layer to the second position.
 19. The method of manufacturinga semiconductor device according to claim 18, wherein before forming thefourth silicon carbide region, the first trench is formed.
 20. Themethod of manufacturing a semiconductor device according to claim 18,wherein a second trench is formed in the silicon carbide layer below theopening by etching the silicon carbide layer by using the mask materialas a mask.